There are 2 microfiche in total, and 103 frames in total.
The present invention relates to computer architectures and particularly those architectures dedicated to the creation of graphical images for printing or displaying.
The creation and printing out of complex images normally proceeds via a description of the image in a page description language (PDL) such as Postscript (trade mark). The page description language normally describes how to construct the output image from a number of primitives and compositing operators. Often, a major advantage of utilizing a page description language is device independence in that the same description can be utilized on multiple output devices taking advantage of those features within the device which can provide advantageous effects. Other advantages include the ability to easily edit or amend portions of the page. Further, optimizations on the PDL can be implemented thereby speeding up the rendering process.
The process of taking a page description and creating a corresponding page for printing from the description is known as rasterization and is often quite taxing of computer resources. Where the PDL interpretation or rasterization process is carried out by a software interpreter running on a host CPU system, the software interpreter is likely to take up a substantial amount of the CPU resource in the creation of each page such that the main host CPU has little time to do anything else. Additionally, the software interpreter is likely to take an excessively long time where each pixel in an image must be decompressed and/or colour converted.
It is known to provide for hardware acceleration of various aspects of the graphical image creation process. For example, hardware JPEG compression/decompression chips are generally available in the market place for performing hardware acceleration of the compression/decompression process.
The type of output device such as a printer or display upon which an image is to be created can be highly variable in its requirements for displaying an image. Some printer devices, once undertaking the printing of a page, require pixel information in respect of the whole page to be provided in advance of printing or within predetermined time periods and are unable to be stopped at any time during the printing of a page. Other output devices operate in a xe2x80x9cbandedxe2x80x9d manner in that one band of the image is printed at a time and an arbitrary time period can occur between bands. Other output devices are able to receive updated pixel information in an arbitrary manner.
A main objective of the present invention is to print out an arbitrary image as fast as possible using various printers or other output devices. In this respect, it is highly desirable to keep the output device xe2x80x9cbusyxe2x80x9d printing (or displaying) and not waiting for the required pixel data. Every time the output device must wait for pixel data, the printing or displaying process will obviously be delayed thereby leading to user frustration. Further, it is also advantageous to ensure that all resources applied to the problem of rasterization are kept fully utilized in productive activity in order to provide a maximised output printing (or display) speed.
Further, depending upon the type of output arrangement utilized, the result can be very susceptible to perceived faults. For example, in some video applications where an image is being continually refreshed, if the new data is not supplied in sufficient time, the old data can be re-displayed and no fault is perceived by the viewer. However, in other video applications, the old image is discarded at the refresh rate and thus if the new image is not available an obvious blank or void is present. With printing, because the resulting image is permanent, any minor defect in the image data often produces a glaring fault. Further, as mentioned above, depending on the nature of the printer, the data must be supplied not only in perfect form but in excess of a predetermined speed. However, with printing a delay before the final image is output can be tolerated.
With the above in mind, it is the object of the present invention to render image data prior to outputting the resulting image by firstly utilizing a graphics co-processor in conjunction with a host processor, and secondly providing two or more instructions streams within the graphics co-processor. If only one of these instruction streams is operated at a time, it has been found that substantial speed advantages result when operating on streams of like image data. This is because the co-processor concentrates on the like sequential calculations and does not lose time in being reset or reconfigured to perform different calculations.
Further, whilst one calculation stream is operating, the other(s) can be reconfigured if necessary in preparation to perform a different calculation.
In accordance with one aspect of the present invention, there is disclosed a method of rendering image data prior to output of the resulting image, said method comprising the steps of:
(1) utilising a graphics co-processor in conjunction with a host processor,
(2) within the graphics co-processor providing a plurality of data calculation streams arranged in parallel fashion, and
(3) operating only one of said data calculation streams at any one time to perform like image calculations on a stream of like image data.
Preferably at least one of the data calculation streams is provided with a reconfigurable calculation unit and at the conclusion of step (3) the reconfigurable calculation unit is reconfigured. In addition the image data is preferably normalized prior to the step (3) being commenced.
In accordance with another aspect of the present invention there is disclosed apparatus for rendering image data prior to outputting the resulting image, said apparatus comprising a graphics co-processor adapted to operation in conjunction with a host processor, said graphics co-processor having a plurality of data calculation streams arranged in parallel fashion but only one of which is operated at any one time to perform like image calculations on a stream of like image data.
Preferably at least one of the data calculation streams has a reconfigurable calculation unit. Preferably a data normalization means is also provided upstream of the parallel data calculation streams.
In the following detailed description, the reader""s attention is directed, in particular, to FIGS. 1, 2, 8 and 9 and their associated description without intending to detract from the disclosure of the remainder of the description.
1.0 Brief Description of the Drawings
2.0 List of Tables
3.0 Description of the Preferred and Other Embodiments
3.1 General Arrangement of Plural Stream Architecture
3.2 Host/Co-processor Queuing
3.3 Register Description of Co-processor
3.4 Format of Plural Streams
3.5 Determine Current Active Stream
3.6 Fetch Instruction of Current Active Stream
3.7 Decode and Execute Instruction
3.8 Update Registers of Instruction Controller
3.9 Semantics of the Register Access Semaphore
3.10 Instruction Controller
3.11 Description of a Modules Local Register File
3.12 Register Read/Write Handling
3.13 Memory Area Read/Write Handling
3.14 CBus Structure
3.15 Co-processor Data Types and Data Manipulation
3.16 Data Normalization Circuit
3.17 Image Processing Operations of Accelator Card
3.17.1 Compositing
3.17.2 Color Space Conversion Instructions
a. Single Output General Color Space (SOGCS) Conversion Mode
b. Multiple Output General Color Space Mode
3.17.3 JPEG Coding/Decoding
a. Encoding
b. Decoding
3.17.4 Table Indexing
3.17.5 Data Coding Instructions
3.17.6 A Fast DCT Apparatus
3.17.7 Huffman Decoder
3.17.8 Image Transformation Instructions
3.17.9 Convolution Instructions
3.17.10 Matrix Multiplication
3.17.11 Halftoning
3.17.12 Hierarchial Image Format Decompression
3.17.13 Memory Copy Instructions
a. General Purpose Data Movement Instructions
b. Local DMA Instructions
3.17.14 Flow Control Instructions
3.18 Modules of the Accelerator Card
3.18.1 Pixel Organizer
3.18.2 MUV Buffer
3.18.3 Result Organizer
3.18.4 Operand Organizers B and C
3.18.5 Main Data Path Unit
3.18.6 Data Cache Controller and Cache
a. Normal Cache Mode
b. The Single Output General Color Space Conversion Mode
c. Multiple Output General Color Space Conversion Mode
d. JPEG Encoding Mode
e. Slow JPEG Decoding Mode
f. Matrix Multiplication Mode
g. Disabled Mode
h. Invalidate Mode
3.18.7 Input Interface Switch
3.18.8 Local Memory Controller
3.18.9 Miscellaneous Module
3.18.10 External Interface Controller
3.18.11 Peripheral Interface Controller
APPENDIX Axe2x80x94Microprogramming
APPENDIX Bxe2x80x94Register tables